Wafer Level 3-D ICS Process Technology Hardcover - 2008
by Chuan Seng Tan (Editor); Ronald J. Gutmann (Editor); L. Rafael Reif (Editor)
From the rear cover
Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration.
Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.
Details
- Title Wafer Level 3-D ICS Process Technology
- Author Chuan Seng Tan (Editor); Ronald J. Gutmann (Editor); L. Rafael Reif (Editor)
- Binding Hardcover
- Edition 1st
- Pages 410
- Volumes 1
- Language ENG
- Publisher Springer
- Date 2008-09-19
- ISBN 9780387765327 / 0387765328
- Weight 1.45 lbs (0.66 kg)
- Dimensions 9.3 x 6.2 x 0.9 in (23.62 x 15.75 x 2.29 cm)
- Library of Congress Catalog Number 2008920894
- Dewey Decimal Code 621.381
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WAFER LEVEL 3-D ICS PROCESS TECHNOLOGY (INTEGRATED CIRCUITS AND SYSTEMS)
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Wafer Level 3-D ICs Process Technology (Integrated Circuits and Systems)
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Wafer Level 3-d Ics Process Technology (integrated Circuits And Systems)
by L. Rafael Reif ,Ronald J. Gutmann ,Chuan Seng Tan ,
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