Logic Synthesis Using Synopsys(r) Hardcover - 1996
by Pran Kurup; Taher Abbasi
From the rear cover
Logic Synthesis Using Synopsys, Second Edition, is for anyone who hates reading manuals but would still like to learn logic synthesis as practiced in the real world. This book should help the reader develop a better understanding of the logic synthesis design flow, optimization strategies using the Design Compiler, test synthesis using the Test Compiler, commonly used interface formats such as EDIF, SDF and PDEF, Links from the Design Compiler to Layout Tools, the FPGA synthesis process, design re-use in a synthesis-based design methodology and a conceptual introduction to behavioral synthesis. Examples in both VHDL and Verilog have been provided throughout the book. Logic Synthesis Using Synopsys, Second Edition covers several new and emerging areas in addition to improvements in the presentation and contents in chapters from the first edition.
Details
- Title Logic Synthesis Using Synopsys(r)
- Author Pran Kurup; Taher Abbasi
- Binding Hardcover
- Edition 2nd
- Pages 322
- Volumes 1
- Language ENG
- Publisher Springer, Boston
- Date 1996-10-31
- Illustrated Yes
- Features Bibliography, Illustrated, Index
- ISBN 9780792397861 / 079239786X
- Weight 1.64 lbs (0.74 kg)
- Dimensions 9.52 x 6.4 x 0.97 in (24.18 x 16.26 x 2.46 cm)
- Library of Congress subjects Computer-aided design, Logic design - Data processing
- Library of Congress Catalog Number 96038284
- Dewey Decimal Code 621.395
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