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High-Level Power Analysis and Optimization

High-Level Power Analysis and Optimization

High-Level Power Analysis and Optimization
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High-Level Power Analysis and Optimization Hardback - 1997

by Dey, Sujit

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Springer, 1997-11-30. 1998. hardcover. New. 7.00x0.50x10.00. Buy with confidence. Excellent Customer Service & Return policy.
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Details

  • Title High-Level Power Analysis and Optimization
  • Author Dey, Sujit
  • Binding Hardback
  • Edition 1998
  • Condition New
  • Pages 175
  • Volumes 1
  • Language ENG
  • Publisher Springer, Boston
  • Publication date 1997-11-30
  • Illustrated Yes
  • Features Bibliography, Illustrated, Index
  • Bookseller's Inventory # DADAX0792380738
  • ISBN 9780792380733 / 0792380738
  • Weight 1.25 lbs (0.57 kg)
  • Dimensions 10 x 7 x 0.5 in (25.40 x 17.78 x 1.27 cm)
  • Size 7.00x0.50x10.00
  • Category Technology & Industrial Arts
  • Library of Congress subjects Integrated circuits - Very large scale, Low voltage integrated circuits -
  • Library of Congress Catalogue Number 97042068
  • Dewey Decimal Code 621.381
  • Quantity available 6

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Reader reviews for High-Level Power Analysis and Optimization

From the publisher

High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.
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