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Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors

Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors

Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors
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Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors Hardback - 2009

by Baer, Jean-Loup

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  • Title Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors
  • Author Baer, Jean-Loup
  • Binding Hardback
  • Edition INTERNATIONAL ED
  • Condition Used - Good
  • Pages 382
  • Volumes 1
  • Language ENG
  • Publisher Cambridge University Press
  • Publication date 2009-12-07
  • Illustrated Yes
  • Features Bibliography, Illustrated, Index, Table of Contents
  • Bookseller's Inventory # 0521769922.G
  • ISBN 9780521769921 / 0521769922
  • Weight 1.85 lbs (0.84 kg)
  • Dimensions 10.1 x 7.1 x 1 in (25.65 x 18.03 x 2.54 cm)
  • Category Computers - General Information
  • Library of Congress subjects Computer architecture, Microprocessors
  • Library of Congress Catalogue Number 2009025686
  • Dewey Decimal Code 004.22
  • Quantity available 1

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From the publisher

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as - the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers - optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations - design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors - state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

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Citations

  • Choice, 06/01/2010, Page 0

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