BIBLIO is the largest independent book marketplace in the world, with over 100 million books.

Skip to content

International Edition

Intl. Ed.

Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors

Intl. Ed.

Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors Hardback - 2009

by Beer

Add to wish list
  • New
  • Paperback
New
International Edition

Description

New/New. Brand New Paperback International Edition, Perfect Condition. Printed in English. Excellent Quality, Service and customer satisfaction guaranteed!
Ask the seller a question Add to wish list
A$47.04
A$21.27 Delivery to USA
Standard delivery: 7 to 14 days
More delivery options
Ships from Students Textbooks (India)

Details

  • Title Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors
  • Author Beer
  • Binding Paperback
  • Edition INTERNATIONAL ED
  • Condition New
  • Pages 382
  • Volumes 1
  • Language ENG
  • Publisher Cambridge University Press
  • Publication date 2009-12-07
  • Illustrated Yes
  • Features Bibliography, Illustrated, Index, Table of Contents
  • Bookseller's Inventory # BIBNNA-12431
  • ISBN 9780521769921 / 0521769922
  • Weight 1.85 lbs (0.84 kg)
  • Dimensions 10.1 x 7.1 x 1 in (25.65 x 18.03 x 2.54 cm)
  • Category Computers - General Information
  • Library of Congress subjects Computer architecture, Microprocessors
  • Library of Congress Catalogue Number 2009025686
  • Dewey Decimal Code 004.22
  • Quantity available 5

About Students Textbooks India

Biblio member since 2009

Selling textbooks, International editions and reference books online from last 5 Years.

Terms of Sale:

30 day return guarantee, with full refund including shipping costs for up to 30 days after delivery if an item arrives misdescribed or damaged. Return address: Students_Textbooks 12 phankha road Jankpuri New Delhi 110036 India

Browse books from Students Textbooks

Reader reviews for Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors

From the publisher

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as - the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers - optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations - design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors - state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

Media reviews

Citations

  • Choice, 06/01/2010, Page 0
tracking-