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MIMO Channel Estimation for FPGA Implementation: Performance and Complexity Improvement of MIMO Channel Estimation for Xilinx Virtex-4 FPGA

MIMO Channel Estimation for FPGA Implementation: Performance and Complexity Improvement of MIMO Channel Estimation for Xilinx Virtex-4 FPGA

MIMO Channel Estimation for FPGA Implementation: Performance and Complexity
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MIMO Channel Estimation for FPGA Implementation: Performance and Complexity Improvement of MIMO Channel Estimation for Xilinx Virtex-4 FPGA Paperback - 2010

by Islam, Mohammad Tariqul

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VDM Verlag, 2010-06-16. paperback. New. 5.91x0.25x8.66. Buy with confidence. Excellent Customer Service & Return policy.
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  • Title MIMO Channel Estimation for FPGA Implementation: Performance and Complexity Improvement of MIMO Channel Estimation for Xilinx Virtex-4 FPGA
  • Author Islam, Mohammad Tariqul
  • Binding Paperback
  • Condition New
  • Pages 108
  • Volumes 1
  • Language ENG
  • Publisher VDM Verlag
  • Publication date 2010-06-16
  • Bookseller's Inventory # DADAX3639267249
  • ISBN 9783639267242 / 3639267249
  • Weight 0.37 lbs (0.17 kg)
  • Dimensions 9 x 6 x 0.26 in (22.86 x 15.24 x 0.66 cm)
  • Size 5.91x0.25x8.66
  • Category Technology & Industrial Arts
  • Quantity available 1

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From the publisher

The context for this book is to present a proficient channel estimation technique for performance improvement and complexity reduction of multiple antenna system. Matrix factorization is applied on LS estimation to reduce a full rank matrix into a simpler form in order to eliminate matrix inversion. Results indicate a significant improvement in SNR compared with LS estimation. The complexity comparison is performed in terms of mathematical operations, which shows that the approach outperforms LS estimation at a lower complexity and represents a good solution for channel estimation technique. The book also provides design and implementation of a multiple antenna system on FPGA that provides reconfigurability, resource utilization and less power consumption. The encoder design is straight forward; however, the decoder design is little tricky as it requires resource optimization. The hardware, presented in this book, utilizes the resources by adopting the technique of parallelism. The system is developed based on modular design which simplifies system design, eases hardware update and facilitates testing the various modules in an independent manner.

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