BIBLIO is the largest independent book marketplace in the world, with over 100 million books.

Skip to content

Network-on-Chip: The Next Generation of System-on-Chip Integration

Network-on-Chip: The Next Generation of System-on-Chip Integration

Network-on-Chip: The Next Generation of System-on-Chip Integration
Click to view full size.

Network-on-Chip: The Next Generation of System-on-Chip Integration Hardback - 2014

by Kundu, Santanu; Chattopadhyay, Santanu

Add to wish list
  • Used
  • Fine
  • Hardback
Used - Fine

Description

CRC Press. Hardcover. 1466565268 Like New; Hardcover; Close to new condition; Covers are still glossy with straight" edge-corners; Unblemished textblock edges; The endpapers and all text pages are bright and unmarked; Binding is tight with a straight spine; This book will be stored and delivered in a sturdy cardboard box with foam padding; Medium Format (8.5" - 9.75" tall); White and red covers with title in black lettering; 2014, CRC Press; 388 pages; "Network-on-Chip: The Next Generation of System-on-Chip Integration," by Santanu Kundu & Santanu Chattopadhyay. . Fine.
Ask the seller a question Add to wish list
A$159.33
A$5.78 Delivery within USA
Standard delivery: 7 to 14 days
More delivery options
Ships from Salish Sea Books (Washington, United States)
Biblio Top Seller
The BIBLIO Guarantee

Details

About Salish Sea Books Washington, United States

Biblio member since 2005

Thank you for taking an interest in one of our books. We specialize in out-of-print or otherwise difficult-to-acquire books. All books are carefully graded. All books are cleaned, checked for binding defects, torn jackets, etc., and any defects are fully corrected before any book is offered for sale. Any defects that cannot be corrected will be mentioned in the description. Major repairs will also be mentioned. All books are shipped in sturdy shipping boxes to prevent unnecessary damage while in transit. Domestic order are shipped with either Delivery Confirmation or Signature Confirmation, the number of which is available upon request. Thanks.

Terms of Sale:

All purchases may be returned for any reason within two weeks of date of receipt. A full refund minus all shipping costs is issued when the book is received back again. If the book has been misrepresented in some way, seller will pay all shipping costs.

Browse books from Salish Sea Books

Reader reviews for Network-on-Chip: The Next Generation of System-on-Chip Integration

Write a review for this book

There are no reviews for this book yet. Be the first to write a review!

Your review will be anonymous unless you login or create an account first.

Overall rating
Remember: You’re rating the book as a work, not the seller or the condition of the specific copy you purchased!

Important Terms and Guidelines

  • Please focus on the book’s content and context. Also, add any personal comments as to how you enjoyed the book. Substantiate your likes and dislikes. You may make comparisons to other books.
  • Reviews must be at least 140 characters in length.
  • Please do not reveal critical plot elements.
  • This is not a help line. Contact customer support if you need help.
Your review must not include:
  • Obscenities, discriminatory language, or other insulting language not suitable for public domain
  • Advertisements, “spam” content, or references to other products, offers or websites.
  • Email addresses, URLs, phone numbers, physical addresses or other contact information.
  • Overly critical comments about other reviews or reviewers
  • Time-sensitive material (i.e. promotional tours, seminars, lectures, etc.)
  • Availability, price, or alternative ordering/shipping information

From the publisher

Addresses the Challenges Associated with System-on-Chip Integration


Network-on-Chip: The Next Generation of System-on-Chip Integration

examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.

Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design.

This text comprises 12 chapters and covers:

  • The evolution of NoC from SoC--its research and developmental challenges
  • NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces
  • The router design strategies followed in NoCs
  • The evaluation mechanism of NoC architectures
  • The application mapping strategies followed in NoCs
  • Low-power design techniques specifically followed in NoCs
  • The signal integrity and reliability issues of NoC
  • The details of NoC testing strategies reported so far
  • The problem of synthesizing application-specific NoCs
  • Reconfigurable NoC design issues
  • Direction of future research and development in the field of NoC


Network-on-Chip: The Next Generation of System-on-Chip Integration

covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.

About the author

Santanu Kundu received his BTech in instrumentation engineering from Vidyasagar University, Medinipur, West Bengal, India, in 2002. He received his MTech in instrumentation and electronics engineering from Jadavpur University, Kolkata, West Bengal, India, in 2006. Immediately after that he joined the electronics and electrical communication engineering department at the Indian Institute of Technology, Kharagpur, West Bengal, India. He received his PhD in 2011. His research interests include network-on-chip architecture design in 2D and 3D environments, performance and cost evaluation, signal integrity in nanometer regime, fault-tolerant schemes, and power-performance-reliability trade-off. He is currently a system-on-chip (SoC) design engineer at LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India.


Santanu Chattopadhyay

received his BE in computer science and technology from Calcutta University (BE College), Kolkata, West Bengal, in 1990. In 1992 and 1996, he received his MTech in computer and information technology and PhD in computer science and engineering, respectively, both from the Indian Institute of Technology (IIT), Kharagpur, West Bengal, India. He is currently a professor in the electronics and electrical communication engineering department at the IIT, Kharagpur. He has contributed to more than 100 publications in refereed international journals and conferences. He has also coauthored and written several textbooks, and is a member of the editorial board of the journal IET Circuits, Devices and Systems.

Please wait a moment while we load the requested page.

tracking-