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Optimal Realization of the Rijndael Algorithm on Xilinx Platforms

Optimal Realization of the Rijndael Algorithm on Xilinx Platforms

Optimal Realization of the Rijndael Algorithm on Xilinx Platforms Paperback - 2015

by Al-Huseiny Muayed Sattar

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Paperback. New. New Book; Fast Shipping from UK; Not signed; Not First Edition; With the spanning of connectedness in every aspect of life, the desire for secure data exchange is at its prime time. This book aims to present an efficient implementation of the Rijndael encryption algorithm (also know as the Advanced
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  • Title Optimal Realization of the Rijndael Algorithm on Xilinx Platforms
  • Author Al-Huseiny Muayed Sattar
  • Binding Paperback
  • Condition New
  • Pages 104
  • Volumes 1
  • Language ENG
  • Publisher LAP Lambert Academic Publishing
  • Publication date 2015-02-23
  • Bookseller's Inventory # ria9783659374517_inp
  • ISBN 9783659374517 / 3659374512
  • Weight 0.36 lbs (0.16 kg)
  • Dimensions 9 x 6 x 0.25 in (22.86 x 15.24 x 0.64 cm)
  • Category Computers - General Information
  • Quantity available 565

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Reader reviews for Optimal Realization of the Rijndael Algorithm on Xilinx Platforms

From the publisher

With the spanning of connectedness in every aspect of life, the desire for secure data exchange is at its prime time. This book aims to present an efficient implementation of the Rijndael encryption algorithm (also know as the Advanced Encryption Standard) on Xilinx FPGA platforms. Initially, we tackle the issue of large look-up tables in the encryption algorithm. Thus, a method for representing the tables in a way that implements efficiently (with low cost, minimal number of stages and high operational speed) is proposed. This involves partitioning the table into four subtables and these tables deliver their contents on two stages. Next, we employ finite fields mathematics to modify the MixColumn operation to be suitable for implementation with basic operations. In addition to that we modify the structure of the algorithm by omitting the operations that the FPGA hardware can execute instantaneously. Similarly we split the operations that are long and slow to facilitate the use of pipline. In this implementation each round of the algorithm is redivided into five stage pipline. The achieved speed is more than 150 MHz with data throughput more than 20Gbps.
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