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Sequential Logic Testing and Verification

Sequential Logic Testing and Verification

Sequential Logic Testing and Verification
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Sequential Logic Testing and Verification Hardback - 1991

by Abhijit Ghosh, Srinivas Devadas, A Richard Newton,

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Details

  • Title Sequential Logic Testing and Verification
  • Author Abhijit Ghosh, Srinivas Devadas, A Richard Newton,
  • Binding Hardback
  • Edition First Edition
  • Condition New
  • Pages 214
  • Volumes 1
  • Language ENG
  • Publisher Springer, Norwell, MA, U.S.A.
  • Publication date 1991-11-30
  • Illustrated Yes
  • Features Bibliography, Illustrated, Index
  • Bookseller's Inventory # 269225
  • ISBN 9780792391883 / 0792391888
  • Weight 1.1 lbs (0.50 kg)
  • Dimensions 9.58 x 6.42 x 0.78 in (24.33 x 16.31 x 1.98 cm)
  • Category Computers - General Information
  • Library of Congress subjects Computer-aided design, Logic design
  • Library of Congress Catalogue Number 91036094
  • Dewey Decimal Code 621.395
  • Quantity available 5

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Reader reviews for Sequential Logic Testing and Verification

From the publisher

In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care- fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte- gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance.
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