BIBLIO is the largest independent book marketplace in the world, with over 100 million books.

Skip to content

Timing Optimization Through Clock Skew Scheduling

Timing Optimization Through Clock Skew Scheduling

Timing Optimization Through Clock Skew Scheduling
Stock photo: cover may vary

Timing Optimization Through Clock Skew Scheduling Hardback - 2008 - 1st Edition

by Taskin, Baris

Add to wish list
  • Used
  • Good
  • Hardback
Used - Good

Description

hardcover. Good. Access codes and supplements are not guaranteed with used items. May be an ex-library book.
Ask the seller a question Add to wish list
A$178.74
Free Delivery within USA
Standard delivery: 7 to 14 days
More delivery options
Dropship order
Ships from Bonita (California, United States)
The BIBLIO Guarantee

Details

  • Title Timing Optimization Through Clock Skew Scheduling
  • Author Taskin, Baris
  • Binding Hardback
  • Edition number 1st
  • Edition 1
  • Condition Used - Good
  • Pages 266
  • Volumes 1
  • Language ENG
  • Publisher Springer, New York, NY
  • Publication date 2008-11-21
  • Illustrated Yes
  • Features Illustrated
  • Bookseller's Inventory # 0387710558.G
  • ISBN 9780387710556 / 0387710558
  • Weight 1.27 lbs (0.58 kg)
  • Dimensions 9.21 x 6.14 x 0.69 in (23.39 x 15.60 x 1.75 cm)
  • Themes
    • Aspects (Academic): Science/Technology Aspects
  • Category Technology & Industrial Arts
  • Library of Congress Catalogue Number 2008937987
  • Dewey Decimal Code 621.395
  • Quantity available 1

About Bonita California, United States

Biblio member since 2020

Terms of Sale: 30 day return guarantee, with full refund including original shipping costs for up to 30 days after delivery if an item arrives misdescribed or damaged.

Browse books from Bonita

Reader reviews for Timing Optimization Through Clock Skew Scheduling

Write a review for this book

There are no reviews for this book yet. Be the first to write a review!

Your review will be anonymous unless you login or create an account first.

Overall rating
Remember: You’re rating the book as a work, not the seller or the condition of the specific copy you purchased!

Important Terms and Guidelines

  • Please focus on the book’s content and context. Also, add any personal comments as to how you enjoyed the book. Substantiate your likes and dislikes. You may make comparisons to other books.
  • Reviews must be at least 140 characters in length.
  • Please do not reveal critical plot elements.
  • This is not a help line. Contact customer support if you need help.
Your review must not include:
  • Obscenities, discriminatory language, or other insulting language not suitable for public domain
  • Advertisements, “spam” content, or references to other products, offers or websites.
  • Email addresses, URLs, phone numbers, physical addresses or other contact information.
  • Overly critical comments about other reviews or reviewers
  • Time-sensitive material (i.e. promotional tours, seminars, lectures, etc.)
  • Availability, price, or alternative ordering/shipping information

From the publisher

The focus of this book is on timing analysis and optimization techniques for circuits with level-sensitive memory elements (registers). Level-sensitive registers are becoming significantly more popular in practice as integrated circuit densities are increasing and the 'performance-per-power' metric for integrated circuits becomes a key issue. Therefore, techniques for understanding level-sensitive based circuits and for optimizing the performance of such circuits are increasingly important. The book contains a linear programming formulation applicable to the timing analysis of large scale circuits. It includes a delay insertion methodology, and offers an overview of circuit partitioning, placement, and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with ultra-modern resonant clocking technology.

From the rear cover

Timing Optimization Through Clock Skew Scheduling focuses on optimizing the timing of large scale, high performance, digital synchronous systems. A particular emphasis is placed on algorithms for non-zero clock skew scheduling to improve the performance and reliability of VLSI circuits.

This research monograph answers the need for a broad introduction to state-of-the-art clock skew scheduling algorithms from a circuit, graph, and mathematical optimization background. A detailed description of clock skew scheduling application on edge-triggered and level-sensitive circuits, synchronized with single and multi-phase clocking schemes, and formulated as linear programming (LP) and quadratic programming (QP) formulations are provided along with an analysis of optimal computer solution techniques. Theoretical limits of improvement in clock frequency through clock skew scheduling are highlighted. Hints and a preliminary implementation of a parallel skew scheduling application are also included.

Timing Optimization Through Clock Skew Scheduling contains sufficient detail for the advanced CAD algorithm developer, researcher and graduate student. Furthermore, with the material provided on timing properties and optimization, those readers with less background can also benefit from this book.

Please wait a moment while we load the requested page.

tracking-