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Timing Optimization Through Clock Skew Scheduling

Timing Optimization Through Clock Skew Scheduling

Timing Optimization Through Clock Skew Scheduling
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Timing Optimization Through Clock Skew Scheduling Hardback - 2008 - 1st Edition

by Ivan S. Kourtev; Baris Taskin; Eby G. Friedman

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Details

  • Title Timing Optimization Through Clock Skew Scheduling
  • Author Ivan S. Kourtev; Baris Taskin; Eby G. Friedman
  • Binding Hardback
  • Edition number 1st
  • Edition 1
  • Condition New
  • Pages 266
  • Volumes 1
  • Language ENG
  • Publisher Springer, New York, NY
  • Publication date 2008-11-21
  • Illustrated Yes
  • Features Illustrated
  • Bookseller's Inventory # BIBNNA-162014
  • ISBN 9780387710556 / 0387710558
  • Weight 1.27 lbs (0.58 kg)
  • Dimensions 9.21 x 6.14 x 0.69 in (23.39 x 15.60 x 1.75 cm)
  • Themes
    • Aspects (Academic): Science/Technology Aspects
  • Category Technology & Industrial Arts
  • Library of Congress Catalogue Number 2008937987
  • Dewey Decimal Code 621.395
  • Quantity available 1

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From the publisher

The focus of this book is on timing analysis and optimization techniques for circuits with level-sensitive memory elements (registers). Level-sensitive registers are becoming significantly more popular in practice as integrated circuit densities are increasing and the 'performance-per-power' metric for integrated circuits becomes a key issue. Therefore, techniques for understanding level-sensitive based circuits and for optimizing the performance of such circuits are increasingly important. The book contains a linear programming formulation applicable to the timing analysis of large scale circuits. It includes a delay insertion methodology, and offers an overview of circuit partitioning, placement, and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with ultra-modern resonant clocking technology.

From the rear cover

Timing Optimization Through Clock Skew Scheduling focuses on optimizing the timing of large scale, high performance, digital synchronous systems. A particular emphasis is placed on algorithms for non-zero clock skew scheduling to improve the performance and reliability of VLSI circuits.

This research monograph answers the need for a broad introduction to state-of-the-art clock skew scheduling algorithms from a circuit, graph, and mathematical optimization background. A detailed description of clock skew scheduling application on edge-triggered and level-sensitive circuits, synchronized with single and multi-phase clocking schemes, and formulated as linear programming (LP) and quadratic programming (QP) formulations are provided along with an analysis of optimal computer solution techniques. Theoretical limits of improvement in clock frequency through clock skew scheduling are highlighted. Hints and a preliminary implementation of a parallel skew scheduling application are also included.

Timing Optimization Through Clock Skew Scheduling contains sufficient detail for the advanced CAD algorithm developer, researcher and graduate student. Furthermore, with the material provided on timing properties and optimization, those readers with less background can also benefit from this book.

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