BIBLIO is the largest independent book marketplace in the world, with over 100 million books.

Skip to content

Timing Optimization Through Clock Skew Scheduling

Timing Optimization Through Clock Skew Scheduling

Timing Optimization Through Clock Skew Scheduling
Stock photo: cover may vary

Timing Optimization Through Clock Skew Scheduling Hardback -

by Ivan S. Kourtev Eby G. Friedman Baris Taskin

Add to wish list
  • New
  • Hardback
New

Description

Springer , pp. 220 . Hardback. New.
Ask the seller a question Add to wish list
A$246.56
A$5.74 Delivery within USA
Standard delivery: 9 to 14 days
More delivery options
Ships from Cold Books (New York, United States)
The BIBLIO Guarantee

Details

  • Title Timing Optimization Through Clock Skew Scheduling
  • Author Ivan S. Kourtev Eby G. Friedman Baris Taskin
  • Binding Hardback
  • Edition First Edition
  • Condition New
  • Pages 194
  • Volumes 1
  • Language ENG
  • Publisher Springer , Boston
  • Publication date pp. 220
  • Illustrated Yes
  • Features Bibliography, Glossary, Illustrated, Index
  • Bookseller's Inventory # 63110198
  • ISBN 9780792377962 / 0792377966
  • Weight 1.08 lbs (0.49 kg)
  • Dimensions 9.6 x 6.42 x 0.7 in (24.38 x 16.31 x 1.78 cm)
  • Themes
    • Aspects (Academic): Science/Technology Aspects
  • Category Technology & Industrial Arts
  • Library of Congress subjects Integrated circuits - Very large scale, Synchronization
  • Library of Congress Catalogue Number 00-20440
  • Dewey Decimal Code 621.395
  • Quantity available 4

About Cold Books New York, United States

Biblio member since 2012

Terms of Sale: 30 day return guarantee, with full refund including shipping costs for up to 30 days after delivery if an item arrives misdescribed or damaged.

Browse books from Cold Books

Reader reviews for Timing Optimization Through Clock Skew Scheduling

Write a review for this book

There are no reviews for this book yet. Be the first to write a review!

Your review will be anonymous unless you login or create an account first.

Overall rating
Remember: You’re rating the book as a work, not the seller or the condition of the specific copy you purchased!

Important Terms and Guidelines

  • Please focus on the book’s content and context. Also, add any personal comments as to how you enjoyed the book. Substantiate your likes and dislikes. You may make comparisons to other books.
  • Reviews must be at least 140 characters in length.
  • Please do not reveal critical plot elements.
  • This is not a help line. Contact customer support if you need help.
Your review must not include:
  • Obscenities, discriminatory language, or other insulting language not suitable for public domain
  • Advertisements, “spam” content, or references to other products, offers or websites.
  • Email addresses, URLs, phone numbers, physical addresses or other contact information.
  • Overly critical comments about other reviews or reviewers
  • Time-sensitive material (i.e. promotional tours, seminars, lectures, etc.)
  • Availability, price, or alternative ordering/shipping information

From the publisher

History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur- rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen- tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta- tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net- work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de- velopments in this area have been slow to reach the designers' desktops.

Please wait a moment while we load the requested page.

tracking-