BIBLIO is the largest independent book marketplace in the world, with over 100 million books.

Skip to content

Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog (The International Series in Engineering and Computer Science)

Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog (The International Series in Engineering and Computer Science)

Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog
Stock photo: cover may vary

Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog (The International Series in Engineering and Computer Science) Hardback - 1999

by Lee, James M

Add to wish list
  • Used
  • Good
  • Hardback
Used - Good

Description

hardcover. Good. Access codes and supplements are not guaranteed with used items. May be an ex-library book.
Ask the seller a question Add to wish list
A$142.58
Free Delivery within USA
Standard delivery: 7 to 14 days
More delivery options
Dropship order
Ships from Bonita (California, United States)
The BIBLIO Guarantee

Details

About Bonita California, United States

Biblio member since 2020

Terms of Sale: 30 day return guarantee, with full refund including original shipping costs for up to 30 days after delivery if an item arrives misdescribed or damaged.

Browse books from Bonita

Reader reviews for Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog (The International Series in Engineering and Computer Science)

Write a review for this book

There are no reviews for this book yet. Be the first to write a review!

Your review will be anonymous unless you login or create an account first.

Overall rating
Remember: You’re rating the book as a work, not the seller or the condition of the specific copy you purchased!

Important Terms and Guidelines

  • Please focus on the book’s content and context. Also, add any personal comments as to how you enjoyed the book. Substantiate your likes and dislikes. You may make comparisons to other books.
  • Reviews must be at least 140 characters in length.
  • Please do not reveal critical plot elements.
  • This is not a help line. Contact customer support if you need help.
Your review must not include:
  • Obscenities, discriminatory language, or other insulting language not suitable for public domain
  • Advertisements, “spam” content, or references to other products, offers or websites.
  • Email addresses, URLs, phone numbers, physical addresses or other contact information.
  • Overly critical comments about other reviews or reviewers
  • Time-sensitive material (i.e. promotional tours, seminars, lectures, etc.)
  • Availability, price, or alternative ordering/shipping information

From the publisher

This work has been revised and updated in accordance with the new IEEE 1364-1999 standard, much of which applies to synthesizable Verilog. New examples have been included as well as additional material added throughout. It focuses on the most commonly used elements of the Verilog Hardware Description Language used by designers for simulation and synthesis of ASICS and FPGAs. It makes learning Verilog easy by following a well proven approach used in the author's classes for many years.

Please wait a moment while we load the requested page.

tracking-