Design-For-Test For Digital IC's and Embedded Core Systems

Upper Saddle River, N.J.: Prentice Hall, 1999. Comprehensive text introduces the basic concepts of test and design-for-test (DFT), and addresses the application of these concepts with an eye toward the trade-offs of the engineering budgets (area, frequency, power, etc.), the business drivers, and the cost drivers. This practical guide on the test and Design-for-test topics has been developed along the lines of a just what you need to know and how to do it guide that explains the topic, the trade-offs, and relates the topic to the design flow. Key topics include: Core-based design, focusing on embedded cores and embedded memories. System-on-a-chip and ultra-large scale integrated design issues. AC scan, at-speed scan, and embedded DFT. Built-in self-test, including memory BIST, logic BIST, and scan BIST. Virtual test sockets and testing in isolation. Design for reuse, including reuse vectors and cores. Test issues being addressed by VSIA and the IEEE P1500 Standard. Design-for-Test for Digital IC's and Embedded Core Systems is filled with full-page graphics taken directly from the author's teaching materials. Every section is illustrated with flow-charts, engineering diagrams, and conceptual summaries to make learning and reference fast and easy. This book is a must for the engineers and managers involved in design and testing. The enclosed Brand-New & Sealed CD-ROM contains full-color versions of all the book's illustrations in Acrobat PDF format. These images may be viewed interactively on screen or printed out to create overheads for teaching. Acrobat Reader software for Windows and UNIX computers is included. 349 pp. Illustrated.. First Edition. Hard Cover. New. 8vo - over 7¾" - 9¾" tall.