Formal Semantics and Proof Techniques for Optimizing VHDL Models Hardback - 1998
by Umamageswaran, Kothanda
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- Hardback
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Details
- Title Formal Semantics and Proof Techniques for Optimizing VHDL Models
- Author Umamageswaran, Kothanda
- Binding Hardback
- Edition U. S. EDITION
- Condition Used - Good
- Pages 158
- Volumes 1
- Language ENG
- Publisher Springer
- Publication date 1998-11-30
- Illustrated Yes
- Features Bibliography, Illustrated, Index
- Bookseller's Inventory # 0792383753.G
- ISBN 9780792383758 / 0792383753
- Weight 0.96 lbs (0.44 kg)
- Dimensions 9.21 x 6.14 x 0.5 in (23.39 x 15.60 x 1.27 cm)
- Category Computers - Languages / Programming
- Library of Congress subjects VHDL (Computer hardware description language)
- Library of Congress Catalogue Number 98045668
- Dewey Decimal Code 621.392
- Quantity available 1
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